Hardware-assisted verification will sprint in new directions at the DATE Conference in Nice, France, this week, where Mentor Graphics Corp. will unveil an "emulation on a chip" architecture for its new Veloce accelerators and emulators, and EVE SA will turn out ZeBu-AX, its next-generation hardware accelerator. Both announcements help move hardware-assisted verification to higher levels of abstraction.

Mentor's new Veloce series claims greatly improved speed, gate capacity, and compilation times compared to its previous VStation Pro and Celaro lines, both of which contributed technology to Veloce. But what Mentor seems proudest of is Veloce's "virtual emulation" or "transaction-based acceleration" technology, which provides a way to compile and test designs from transaction-level testbenches, and requires no connection to physical hardware.

EVE's ZeBu-AX represents the company's first release of acceleration technology acquired from Tharas Systems earlier this year, but it claims significant capacity and compilation advantages over Tharas' Hammer accelerator line. It also adds a transaction-level, C language capability.

Veloce may challenge some traditional notions of how hardware-assisted verification is used, and how it's defined. Gary Smith, chief analyst at Gary Smith EDA, has noted that acceleration and emulation have been divided into less expensive, easier to use "design team" products and more expensive, and powerful, "emulation team" products run by separate organizations.

"Mentor is attempting to use a building block approach to acceleration and emulation, in effect eliminating the emulation team category," Smith said. Mentor provides three tiers within the Veloce family – Trio, Solo, and Quattro – representing different levels of capacity and capability.

But the "exciting part" of the Veloce announcement, Smith said, is "that they are moving A&E [acceleration and emulation] up to the ES [electronic system] level with their transaction level capability." That capability appears to blur the line between acceleration, which traditionally speeds software simulation, and emulation, which typically implies that users are running tests on actual hardware.

A driving force behind the transaction-level approach is the Accellera Standard Co-Emulation Modeling Interface (SCE-MI) standard, which allows transaction-level verification between different hardware and software simulation and emulation environments. Mentor claims support for the draft SCE-MI 2.0 standard, and EVE claims partial support.

Both companies will be competing with Cadence Design Systems, which led the acceleration and emulation market in the most recent Gartner Dataquest surveys. Cadence's Xtreme III accelerator and emulator, introduced last fall, supports up to 72 million gates in one chassis, and lets designers run transaction-based acceleration using the current SCE-MI 1.1 standard.

Bigger and faster

Mentor claims that Veloce runs at speeds up to 1.5 MHz, 3 to 5 times faster than previous generation Mentor acceleration and emulation systems. The company claims compile times of 15 million RTL gates per hour, about three times that of VStation Pro. Veloce provides capacity up to 128 million ASIC gates, compared to 60 million for VStation Pro.

Driving Veloce is an "emulation on chip" that claims to combine the advantages of Celaro's custom ASIC approach, which brought fast compile times and interactive debugging, and VStation's FPGA-based approach, which could handle asynchronous clock domains. The result, said Sanjay Sawant, director of marketing for Mentor's emulation division, is a chip with a "reconfigurable fabric" implemented inside a custom system-on-chip (SoC). The VStation Pro "virtual wires" emulation technology, previously implemented in software, is now on the chip.