NICE, France — A panel of experts, moderated by EDA analyst Gary Smith, tried to wrestle with the task of "bridging the FPSoC divide" on the first day of the DATE exhibition and conference.

The panel included Eric Filseth, corporate vice president of product marketing at Cadence Design Systems Inc.; Ralph von Vignau, senior director at NXP BV; Vittorio Peduto, general manager of the computer systems division at STMicroelectronics NV; Torhu Furuyama, general manager of the center for semiconductor R&D at Toshiba Corp.

The lack of a conclusion from such an illustrious panel was a testament to the challenges that beset the manufacturers and system-level developers at the leading edge of complexity.

Peduto and Furuyama both made the point that hybrid field-programmable chips are out there in the field; the Spear family from STMicroelectronics with up to 600,000 field-programmable gates and a couple of ARM processor cores, and the MEP multimedia processor from Toshiba, which incorporates a field-programmable fabric originally developed at startup company Elixent Ltd.

However, these offerings are the exceptions in an otherwise sparsely populated area of manufacturing. Cadence's Filseth made the point that the market has voted for maximum quality of results — in the form of processors running software and FPGAs or maximum performance in the form of system chips (SoCs) "with nothing much in between"

The gate array market, although it continues to exist for legacy products, has ceased growing and the structured ASIC market has been a "start, stop, start, stop market," according to Filseth. Filseth spoke up for "spare cell remapping" as one way of producing design respins that only required metal changes and which can be done without impact on QoR, but admitted that it only applied to relatively small changes.

It was left to von Vignau, from platform advocate NXP to try and bridge the divide. And with NXP's background in consumer electronics, it was perhaps to be expected that he would come down on the side of QoR and processors running software. . With regard to applying field-programmable fabric patches von Vignau said: "Do you prevent respins? I don't believe so. Two thirds of your development cost is verification cost and the more you put on the IC the harder verification becomes. Field programmable hardware chips are not really practical in high volume applications. I do believe in standard structures; microprocessors, DSPs, with programmability via software."

Von Vignau went on to indicate the real challenge that was coming was in accommodating multiprocessor architectures as processors and system-chips converge. "It is parallel processing that is the future," said von Vignau

In this he was strongly supported by Smith who also drew the distinction between heterogeneous and homogeneous processor arrays and the need for information technology to break out of the constraints set by John von Neumann and his theories of computer architecture from the twentieth century and the C language.