NICE, France – The demand for analog/mixed-signal intellectual property (IP) blocks has never been greater, especially at the 65-nm process node and below. At a panel discussion at the DATE conference this week in Nice, France, speakers called for a new breed of analog designers who would be able to face the power dissipation constraints, due to the increased leakage, device variability and model accuracy, and new design methodologies and tools for enhanced reliability.

“Today, at the 90-nm process node, we are able to integrate multiple cores on systems-on-chip (SoCs), and the percentage of SoCs with mixed-signal content is growing from about 10 percent in 1998 to about 70 to 80 percent in 2006,” declared Georges Gielen, a professor at Katholieke Universiteit in Leuven (Belgium) and moderator of the panel.

The bad message, he continued, is that the productivity of analog designers is quite low. It is estimated at about 1 device per hour compared to thousands of devices per hour on the digital side. Moving to the 65-nm process node and below, he identified new obstacles. The supply chain is dropping. The variability is becoming a problem in analog circuits. And, as we integrate different blocks in the circuit, interferences limit its performance.

Similarly, Christian Münker of Infineon Technologies AG (Munich, Germany), who sees new opportunities by integrating analog and RF components on chips, said the main issue for the 65-nm node is complexity, and more precisely design complexity with a growing need for EDA flow and support and design process complexity.

“The design methods have to be changed for analog circuits at 65-nm and below,” replied Joachim Kunkel, Reimund Wittmann, project manager at Nokia Research center in Bochum (Germany). “As the number of constraints are rising, there is a need for automated analog processes, and analog designers need full control of the design process.”

Massimo Vanzi, CEO of Accent SpA, (Vimercate, Italy), joint venture design house and IP licensor formed by STMicroelectronics and Cadence Design Systems Inc., said that 80 percent of the company’s product developments in 2006 included significant analog functions, and noted that, despite challenges and issues, the trend to structured mixed-signal SoC design is unstoppable. In this context, he said he did not see the 65-nm process node as a major stopper.

However, Vanzi indicated that today’s analog IP market requires design specifications, simulation environment, silicon characterization, design schematics, additional CAD views, VSIA quality assessment sheet, test program and customized program. He added that AHDL IP model and self-test features in the analog domain, as they exist in the digital domain, would be quite appreciated.

“At Accent, we see less and less the need to move to advanced silicon technology nodes,” he commented. “Our biggest challenge is the product integration of heterogeneous technologies working together.”

On a different level, Joachim Kunkel, vice president and general manager of the System Level Design business unit of Synopsys Inc. (Mountain View, California) explained that the digital SoC content is forcing the analog, mixed-signal content to smaller process geometry nodes. “The question is not whether you can design analog, mixed-signal IP for the 65-nm process node but whether you can do it efficiently enough to make a business,” he declared.

As a conclusion, he stressed that “at Synopsys, we are off to the 45-nm process node, and the new frontier for us consists in making RF IPs.”