True design for manufacturability (DFM) at 65-nm and below technology nodes has become more critical due to the shrinking of the critical dimensions of structures on the chip where the same absolute physical variations can result in relatively large electrical variations.

At 65 nm and below, lithographic effects become the biggest contributor to manufacturing variability. The problem is that the features (structures) on the silicon chip are now smaller than the wavelength of the light used to create them. If a feature were replicated as-is in the photomask based on the lithographic image, the corresponding form appearing on the silicon would drift farther and farther from the ideal, with the decreasing feature sizes associated with the newer technology nodes.

The way this is currently addressed in conventional design flows is to postprocess the GDSII file with a variety of reticle enhancements techniques (RETs), such as optical proximity correction and phase-shift mask. For example, the physical design tool modifies the GDSII file by augmenting existing features or adding new features, known as subresolution assist features, to obtain better printability. This means that if the tool projects that the printing process will be distorted in a certain way, it can add its own distortion in the opposite direction, attempting to make the two distortions cancel each other out.

The issue is that every structure in the design is affected by other structures in close proximity. That is, if two geometric shapes are created in the GDSII file and photomask in isolation, these shapes print in a certain way. But if the same shapes are now located in close proximity to each other, interference effects between these shapes modify each of the shapes, often in nonintuitive ways. The results of all these effects are variations in timing, noise, power consumption and, ultimately, yield.

Click here for larger image

Manufacturing and yield problems typically fall into four main categories: catastrophic, parametric, systematic (feature-driven) and statistical (random). Catastrophic problems are those such as a missing via, which cause the chip to fail completely. By comparison, parametric problems leave the chip functioning, but out of its specified range, such as a 500-MHz device that runs at only 300 MHz, or a part that is required to consume less than 5 W of power that actually consumes 8W. The origins of both catastrophic and parametric problems can be subdivided into systematic (feature-driven) effects and statistical (random) occurrences.

A true DFM-aware solution has to address each of these problem categories, which means that it must be able to model all systematic and statistical effects during implementation, analysis, optimization and verification.

The way to reach acceptable performance and yield goals is to make the entire design flow, including cell characterization, IC implementation, analysis, optimization and sign-off, DFM-aware. Within such a flow, manufacturability issues are understood and addressed at the most appropriate and efficient step, creating tighter links between design and manufacturing so that design intent feeds forward to manufacturing, while fab data feeds back to design.

Design tools (particularly the implementation, analysis and optimization engines) have traditionally been rules-based. That means they were provided with a set of rules and they analyzed and modified the design to ensure that none of the rules were violated. In today's ultra-deep submicron technologies, however, these rules no longer reflect the underlying physics of the fabrication process. Even if the design tools meticulously follow all of the rules provided by the foundry, the ensuing chips can still exhibit parametric (or even catastrophic) problems.

To address these problems, tools now need to employ model-based techniques. This means that the tools model the way in which the chips will actually be fabricated. In lithographic simulations, for example, the tools model the way in which light will pass through the photomasks and any lenses, as well as how it will react with the chemicals on the surface of the silicon chip and how the resulting structures will be created.

A true DFM-aware design environment begins with DFM-aware characterization. This involves taking the various files associated with the standard-cell libraries, along with the process design kit and DFM data and models provided by the foundry, and then characterizing the libraries with respect to process variations and lithographic effects to create statistical probability density functions in the context of timing, power, noise and yield. As part of this process, a variety of technology rules are automatically extracted and/or generated for use by downstream tools.

A true DFM-aware characterization environment also provides yield scoring for individual cells, taking into account chemical mechanical polishing effects and using techniques like critical-area analysis to account for random particulate defects. This allows the model characterization process to provide both sensitivity and robustness metrics that can be subsequently exploited by the implementation, analysis and optimization engines. By knowing the delay or leakage sensitivity of each cell, for example, the implementation tool can optimize critical timing paths by avoiding such cells, or by altering their placement to minimize such sensitivity.

Conventional synthesis engines perform their selections and optimizations based on the timing, area and power characteristics of the various cells in the library, coupled with the design constraints provided by the designer. In a DFM-aware environment, the synthesis engine takes into account each cell's noise and yield characteristics, and the variability characteristics (process and lithographic) of the cells forming the library and the way in which these characteristics affect each cell's timing, power, noise and yield.