PARIS — EDA startup Elastix Corp. (Santa Clara, Calif.) is aiming to address digital IC variability issues by helping designers generate asynchronous implementations of synchronous designs automatically. Early versions of Elastix software have been put out for evaluation with selected customers. The final EDA product - the name remains undisclosed — is due to be introduced more broadly in 2008.

Elastix' potential customers are the world’s main semiconductor manufacturers. Vigyan Singhal, founder, president and CEO said Elastix already "has access to semi companies in Europe such as NXP, Infineon and ST."

Variability is becoming a cause of chip failures and delayed schedules at nanometer geometries. Either intense engineering effort must be applied just to achieve acceptable yields or engineers can increase the guard-banding in design rules. But this can often negate most of the benefits of going to smaller geometries. Intelligent application of variability-aware design, for example applying guard-banding strongly only on critical portions of a design is now being supported by a number of EDA companies.

Elastix has decided to address the issue by way of manipulating the clock signal. The company claims that for any synthesizable digital design its design-for-variability technology can generate an asynchronous physical implementation that responds automatically to variability, and self-adjusts according to process, voltage, and to temperature and logic conditions. Work started at the Software Department of the Universitat Politecnica de Catalunya (LSI-UPC) in Barcelona, Spain and continues at Elastix' recently-opened R&D center in Barcelona.

Variability in ICs has three root causes: variation of environmental parameters such as supply voltage and temperature, variations in manufacturing processes implying device and interconnect changes and reliability causes like "wear-out" or "device aging" phenomena such as negative biased thermal instability and hot carrier degradation.

"Variability comes in many forms but all are caused by the small changes in the silicon process, the chemical mechanical planarization, the lithography and so on, and it becomes more pronounced as the geometries shrink," said Gary Smith, founder and chief analyst for Gary Smith EDA (Santa Clara, Calif.), saying that highest causes of concern are power and timing. "And, we are expecting variability to become critical at 32-nm," he added.