LONDON — EDA startup Elastix Corp. (Santa Clara, Calif.), which is pioneering the use of variable clocking as an asynchronous means of improving performance and power-efficiency of classically design circuits, has agreed to to work with Newcastle University in the northeast of England, one of the leading centers of asynchronous logic research.

Vigyan Singhal, CEO of Elastix, said his company would provide tool licenses to students, of Professor Alex Yakovlev. Prof. Yakovlev heads up the Microelectronic Systems Design research group at Newcastle University's School of Electrical, Electronic and Computer Engineering. The students would then use the tool for research activities and to extend its scope.

"We intend to investigate new application areas for asynchronous chips, such as the security advantages for electronic chips in secure systems such as payment and access control facilities," said Singhal.

Although headquartered in Santa Clara, Elastix has its R&D base in Barcelona near to the University Politechnica Calalunya, where Jordi Cortadella did much of the early research into elastic clocking.

Prof. Yakovlev said that the Newcastle University asynchronous design group was one of the largest in the world and was on a similar level to the University of Manchester, also in England. He added that there is a core research team of about 10 people and as many as 20 researchers in all, studying asynchronous logic. "Asynch should be regarded in a broad context." "Recent work by Alex's group has shown how to use asynchronous logic to enhance the security of smartcards," said Singhal. This is in the form of a counter measure against energy consumption profiling, which is used to help break encryption.

Singhal said the licensing of the Elastix design tool at Newcastle University was in parallel with commercial deployments in the United States and Europe. He said this was an expansion of the R&D base and could result in a office being opened in Newcastle and smoother uptake up of students into Elastix. "Variability has created barriers to making faster chips and lower power chips. The asynchronous expertise that can help address this is not easily available," Singhal said.

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