PARIS — The electronics design community is meeting the challenges for greener and more environmentally friendly electronic devices and systems. This was one of the main messages from the SAME Forum held last month in Sophia Antipolis, France. The challenges are perhaps greatest for low-power designs, especially in complex mixed-signal SoCs to provide designers with a higher degree of system-level capability in EDA tools.

At the Forum, EDA executives reported on progress in automating the low-power design and verification flow at higher levels of abstraction.

Power is inseparable from the existing aspects of chip design, stated Ted Vucurevich, CTO of advanced R&D at Cadence Design Systems Inc. (San Jose, Calif.). For instance, he stressed, chip performance and function are deeply impacted by choices related to power optimization. "Therefore, it is imperative that a holistic view of the design be used, rather than attempting to tack on power as a side consideration. Power is simply too intertwined with timing, area and function to be treated in a vacuum."

There are different ways of reducing power, noted Jean-Marie Saint-Paul, European manager for system-level and verification solutions at Mentor Graphics Corp. (Wilsonville, Ore.). "But, if we want to be efficient we have to work at the system level and look at the system as a whole. If you try to model the system, you need to bring people with software, mathematical algorithms or mechanical knowledge and make them talk together. Today, people in the industry are not talking to find a solution."

Keeping to the specifics of verification, Vucurevich highlighted key issues that users face on low-power design. They seek to understand the importance of the design function caused by the overlapping power reduction strategy, to estimate the effectiveness of the power reduction strategy as early as possible in the design process, to ensure proper operation of the power features of the design and, finally, to verify the fidelity of the implementation of the power strategy.

"At the implementation level, the bottlenecks in the low-power flow are turning out to be the same old bottlenecks, but simply exacerbated," he stated. "Functional verification is now more difficult because of the added dimension of power-related behavior overlaid on the already hyper complex problem. Timing closure is more acute as design teams seek to squeeze out unnecessary overpowering and power budgets are being tightened down."