Santa Cruz, Calif. — Silicon on insulator (SOI) can offer substantial performance and power advantages over bulk CMOS, but cost concerns and design issues have largely kept it out of the ASIC market. That's about to change, predicts intellectual-property provider Silicon On Insulator Systems and Integrated Circuits (Soisic).

Soisic (Grenoble, France) this week will announce that it has the industry's first customer-owned tooling (COT) SOI design kit, aimed at a 90-nanometer Freescale process. Armed with SOI-specific multi-Vt standard cell libraries, memory compilers and standard I/Os, ASIC designers can now jump on the SOI bandwagon using existing design tools and methodologies, Soisic maintains.

The advantages over CMOS can be substantial: up to 35 percent better performance and up to 50 percent power savings, based on comparisons run by Soisic. But SOI wafer costs can be as much as 20 percent higher, and one design kit does not create an infrastructure with a choice of foundries and third-party IP blocks.

"This is the first time a COT [SOI] design kit has been available," said Eduard Weichselbaumer, Soisic CEO. "Before, people had to use proprietary tools and internal methodologies. You would have to go to an IBM or a Freescale and use their infrastructure, which is very, very difficult."

Dave Cavanaugh, director of manufacturing at Semico Research Corp., noted that the current cost of an SOI device is about three times that of a CMOS device. Most of that, he said, is due to design issues. "If Soisic is successful, they will substantially reduce the costs of design," he said. "At 45 nm and below, the physics of SOI technology will become compelling."

Those physics have led several microprocessor providers to embrace SOI. They include IBM, which used SOI to develop its Cell processor. SOI manufacturing is offered by a number of providers, including IBM, Sony, Toshiba, Chartered, Renesas, Freescale, ST Microelectronics, Philips and TSMC.

But SOI requires recharacterized cell libraries, largely because of the difficulty of modeling what is called the floating-body effect. With SOI technology, an electrically isolated transistor body can affect the threshold voltage of the transistor. It can deliver a huge performance gain, but it greatly complicates timing analysis.