Austin, Texas -- Semiconductor researchers are pursuing an emerging memory type that uses the floating-body effect of silicon-on-insulator (SOI) technology as the memory storage mechanism. At last month's Symposium on VLSI Circuits, Renesas Technology Corp. and Toshiba Corp. described progress with their floating-body memory (FB-RAM) development efforts, aimed at embedding fast and dense DRAM on logic chips that require lots of on-board memory.

Earlier this year, Advanced Micro Devices Inc. agreed to license the Z-RAM (zero capacitor, one transistor) technology from Innovative Silicon Inc., a Santa Clara, Calif.-based startup with its engineering team in Lausanne, Switzerland.

Floating-body memory is still years away from commercial use, however. "Companies may do SOI-based products, but I don't think they will put floating-body RAM on SOI until at least the 25-nm node," said Sreedhar Natarajan, president of Emerging Memory Technologies Inc. (Ottowa) and the author of a book on SOI chip design.

The FB-RAM is "basically a small, cheap embedded DRAM--it is not an SRAM replacement," said Suresh Venkatesan, a director of silicon technology solutions at Freescale Semiconductor Inc. "With any embedded DRAM, you have to go through the process of seeing where it fits. The question is, now that it is smaller and cheaper, does it open up more application spaces than the old embedded DRAM?"

Venkatesan foresees a decade's worth of development ahead. "Any new material or technology, in my opinion, will take eight or 10 years [to perfect]," he said.

FB-RAM does away with the capacitor used in conventional DRAM bit cells built in bulk silicon. In bulk CMOS, the charge that forms a transistor's body is tied to a fixed voltage. In SOI, the untied body is "floating" in silicon above the thick oxide layer. To make the floating body behave like a capacitor, a carefully controlled voltage is applied on both sides of the body.

For companies that start out with SOI wafers for their high-performance processors, such as AMD, IBM or Freescale, the FB-RAM approach has several advantages: fast read and write times, and a cell size smaller than embedded DRAM and about one-fifth that of a six-transistor SRAM. With the trench and stacked capacitors of conventional embedded DRAM becoming more difficult to build, proponents claim that FB-RAMs are cheaper, and require few additional mask layers.

There are challenges. Since the floating body is not tied to a fixed voltage, the stored charge can easily fluctuate if the reference voltage is not strictly controlled. As CMOS scales to 45 nanometers and below, controlling transistor and voltage variation is becoming more difficult, including variations in FB-RAMs. If the voltage fluctuates, plus or minus, by 0.5 V, the FB-RAM transistor can lose charge.

Like SRAMs and DRAMs, FB-RAMs are volatile--data is lost when the system powers down, so FB-RAMs must be refreshed every few hundred milliseconds. But they do not need to be restored in the same way as DRAMs, which require data to be restored after the destructive DRAM read cycle.

At the Symposium on VLSI Circuits, Toshiba engineer Takashi Ohsawa said the company's 128-Mbit floating-body cell (FBC) test chip demonstrated a nearly 100 percent bit yield. The cell size of 0.17 square microns is half that of comparable embedded-DRAM bit cells. "Scaling is easier than with conventional embedded DRAM," Ohsawa said. "With DRAMs, the process cost is getting high because of the deep-trench capacitor." With FBC, however, "it is important to have an accurate reference voltage." In the Toshiba FBC, the write time was consistently measured at 10 nanoseconds or less.

Also at the symposium, Renesas discussed an enhanced twin-transistor RAM based on an SOI technology. Though the design has a larger cell size than the single-transistor FB-RAM approach, Renesas said that it is less costly to build, with fewer process changes. Also, the company claims that the so-called eT²RAM is better-suited to modern system-on-chip (SoC) solutions, which rely on multiple voltages and other power-management schemes to keep power consumption under control. "This could be a mainstream memory for advanced SoCs," said Kazutami Arimoto, a Renesas engineering manager.

The company recently fabricated a 4-Mbit test chip using a 90-nm SOI process, and a full evaluation is under way. With the two-transistor architecture, the eT²RAM operated successfully with a 0.5-V power supply, achieving a respectable 56-MHz operation at such a low operating voltage.

If a high-k dielectric and metal gate electrode were used in the transistor, the cell size could be scaled further--partly because the high-k dielectric can be physically thicker and transistor variability can be better controlled, Arimoto said.

Since Renesas--ranked as the world's largest microcontroller vendor--does not have a line of high-performance MPUs that use SOI technology, one challenge is to find a home for its SOI-based eT²RAM.

In May, Emerging Memory Technologies Inc., which provides memory design services and intellectual property, took a license. EMT is betting that SOI will expand beyond the high-performance MPU niche into the broader semiconductor market, company president Natarajan said.

"Customers will eat the area penalty with the Renesas twin-transistor approach if the thing actually works," he said. "The data retention is better, the performance is better, the yield is better and it doesn't need a high-voltage [prevention] mask. The high voltages also become a reliability issue."

Renesas is working to adapt the twin-transistor RAM process to an SOI process at a major foundry in Taiwan, so that potential customers can evaluate it.

Meanwhile, Venkatesan said Freescale has been evaluating the Innovative Silicon approach to FB-RAM, adding that the company has not taken a license from ISI at this point. "We continue to evaluate the technology for our own set of applications. ISI has some ideas about how certain things can be done to avoid some of the issues that one could potentially face with a memory type of that nature," he said.

The drawback of the FB-RAM is that it is fundamentally available only on an SOI substrate, which limits the number of applications. Network processors, for example, are not well-suited to embedded DRAM, Venkatesan said, because many NPUs are crammed onto line cards, making it difficult to partition the memory. For high-performance CPUs, which face memory limitations going forward, the FB-RAM could not be used to replace SRAM in the Level 1 cache, which must run at multiple gigahertz.

"With floating-body RAM you have to look for a system architecture that makes it attractive to have large amounts of memory on-chip that doesn't need to be accessed within the clock cycle, or which can be accessed with much higher latency," Venkatesan said. "One example might be pulling in some off-chip DRAM back onto the processor. One has to take a look at what this technology brings to the table and then do things differently in terms of how you partition the memory. That's a process of understanding that takes time."

FB-RAMs are in the early stage of development, and it will take time to explore the reliability issues, he added. "The memory incumbents [DRAM, SRAM and flash] have been around for three decades or more, and we understand their reliability. With any new technology, there is the whole piece of understanding the reliability issues and scaling path," he said. "It took Freescale 10 to 12 years to get its MRAM to the point of commercial introduction [see July 10, page 1]. It took us 10 years to bring SOI to the market. It took us 10 years for copper interconnects." Venkatesan thinks FB-RAM faces the same development curve.

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