LONDON — Semiconductor Insights Inc., a Canadian engineering consultancy, has dissected a 50-nanometer NAND flash memory from IM Flash Technologies (IMFT) and concluded that although it is the first 50-nanometer memory it still trails a 70-nm part from Toshiba in memory density.

Semiconductor Insights (Kanata, Ontario), which analyzes integrated circuits, devices structures and patent portfolios., said the 50-nm NAND flash memory from IMFT, a joint venture between Intel Corp. (Santa Clara, Calif.) and Micron Technology Inc. (Boise, Idaho), still trails the Toshiba 70-nm 8-Gbit device because it is single-bit per cell device.

The IMFT 4-Gbit device offers 41.8-Mbits of storage per square millimeter of silicon die compared with 56.5-Mbit per square millimeter density offered by Toshiba's 70-nm 8-Gbit NAND flash memory, which is enabled by its multilevel cell (MLC) implementation.

"Our preliminary analyses of the [IMFT] device has confirmed a 50-nm gate length in the word-line pitch," said Geoff MacGillivary, SI's lead memory analyst, in a statement. "This is the most advanced flash part we've seen to date and we are impressed that IMFT has been able to ramp up so quickly to such a small lithography process technology."

MacGillivary said that Samsung's 65-nm 4-Gbit NAND flash had been the previous leading single-level cell (SLC) memory with a density of 31.3-Mbit per square millimeter. The IMFT has a 30 percent smaller die area than the Samsung device. "The only device that exceeds IMFT's solution is Toshiba's 70-nm 8-Gbit NAND flash at 56.53-Mbit per square millimeter, due to its multilevel cell (MLC) implementation. However, this is accomplished in a die nearly 50 percent larger than IMFT's, which affects the total cost to manufacture," said MacGillivray.

Additional details of the Samsung and Toshiba flash memory devices were discussed in an article published on June 19, 2006.